The invention relates to output circuits for integrated circuits (ICs). More particularly, the invention relates to a configurable bus hold circuit having only a small and transitory leakage current.
Integrated circuits (ICs) are growing denser and faster with every product generation. As ICs pack more and more circuitry into the same amount of silicon area and operate at higher and higher speeds, the power consumption increases rapidly. Increased power consumption is undesirable for several reasons. For example, high power consumption makes a device unsuitable for applications that run on battery power. In addition, high power consumption causes a device to give off large amounts of heat, which can be difficult and expensive to dissipate.
One method of lowering the power consumption of an IC is to decrease the operating voltage. Therefore, IC operating voltages have been steadily dropping over the years. Where once virtually all ICs operated at 5 volts, operating voltages of 3.3 volts and 2.5 volts are now common, and 1.8 volt ICs are also available. Because of this wide range of operating voltages, many ICs are designed to interface with other ICs operating at different voltage levels.
Another method of reducing power consumption is to reduce the leakage current in the device. Output circuits are significant contributors to leakage current in traditional ICs. In addition to traditional output drivers, output circuits include, for example, weak pull-up circuits and bus hold circuits.
A weak pull-up circuit (also called a xe2x80x9cweak keeperxe2x80x9d) keeps a high voltage on an output node when no other driver is pulling the node low. Weak pull-up circuits are traditionally implemented simply by adding a weak pull-up to the output node (i.e., by inserting a small P-channel transistor, gated by ground, between the output node and power high). Because the pull-up is deliberately weak, another driver (e.g., a driver on another IC coupled to the same output node) can drive the output node low by turning on a path of normal strength between the output node and ground. However, when a pull-down is active (i.e., turned on) on the output node, the weak pull-up in series with the active pull-down provides a path between power high and ground. The resulting leakage current can be significant, particularly in today""s high pad-count ICs that support wide data and address busses.
A bus hold circuit also acts to keep an output node at a known value when no other driver is active. However, a bus hold circuit is different from a weak pull-up circuit in that a bus hold circuit retains whatever value was previously on the output node. For example, if a driver on the same or another IC places a low value on the node and is then tri-stated, the bus hold circuit retains the low value on the node. Similarly, if an output driver places a high value on the node and is then tri-stated, the bus hold circuit retains the high value on the node. A bus hold circuit is traditionally implemented as a latch, e.g., as a pair of cross-coupled inverters, with one of the two inverters being a weak inverter that drives the output node.
Therefore, it is desirable to provide a configurable output circuit that provides both weak pull-up and bus hold functions and is operable at a variety of voltage levels, including lower voltages than may be placed on the output node by other drivers. It is further desirable to minimize leakage current in the configurable output circuit.
The invention provides an output circuit configurably providing a bus-hold function and a weak pull-up function, while having only a transitory leakage current through the circuit regardless of the voltage level on the pad. Thus, the output circuit of the invention can be used in low-voltage devices that interface with higher-voltage devices without paying the penalty of increased leakage current.
One embodiment of the invention includes a circuit output node coupled to a configurable weak pull-up circuit, a configurable bus hold circuit, and a configurable leakage prevention circuit.
The configurable weak pull-up circuit includes a weak pull-up coupled between the circuit output node and a power high, and a P-channel transistor coupled in series with the weak pull-up between the circuit output node and the power high. The P-channel transistor is controlled by a configuration signal to enable or disable current flow through the weak pull-up.
The configurable bus hold circuit includes first and second cross-coupled inverters. The second inverter drives the circuit output node. Thus, the two inverters function as a latch that holds the current value on the circuit output node. Each inverter can be disabled (isolated from power high and/or ground) using configuration signals, to disable the bus hold circuit.
The configurable leakage prevention circuit permits only transitory leakage current through the output circuit, regardless of the value of a voltage level externally driven onto the pad.
The configurable leakage prevention circuit includes an N-channel transistor coupled between first and second nodes, where the first node and a gate terminal of the N-channel transistor are coupled to power high. Thus, in the absence of any other stimulus, the second node is at a voltage level one N-channel transistor threshold below the power high level. Also included is a first P-channel transistor coupled between the second node and the circuit output node. A gate terminal of the first P-channel transistor is also coupled to power high. The second node gates a second P-channel transistor on a pull-up path of the output node.
In the absence of the leakage prevention circuit, and when the weak pull-up circuit is disabled, but an external source is driving the circuit output node to a level higher than power high minus one P-channel threshold voltage level, leakage current would occur through the weak pull-up circuit. The leakage prevention circuit prevents this leakage by ensuring that the second P-channel transistor (which is on the weak pull-up path) is fully off under these conditions.
In one embodiment of the invention, the configurable output circuit is implemented as a portion of a programmable logic device (PLD), and the configuration signals are programmed into configuration memory cells as part of the configuration of the PLD.